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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:30:25 03/30/2012 
-- Design Name: 
-- Module Name:    mux_2to1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux_2to1 is
	generic (width : integer := 8);
	port ( d0 : in  STD_LOGIC_VECTOR (width-1 downto 0);
          d1 : in  STD_LOGIC_VECTOR (width-1 downto 0);
			  s : in  STD_LOGIC;
           y : out  STD_LOGIC_VECTOR (width-1 downto 0));
end mux_2to1;

architecture Behavioral of mux_2to1 is

begin

	y <= d0 when  s = '0' else d1;

end Behavioral;

--	PARA INSTANCIARLO ESPECIFICANDO EL SIZE.
--nombre: mux_2to1 generic map (size) port map (d0,d1,s,y);